Gallium arsenide (GaAs) and other III-V alloys have exhibited great potential for high power and/or high frequency electronic applications. Particularly desirable applications include high electron mobility transistors (HEMTs), which are electronic devices having three terminals including a gate, a drain, and a source. The HEMT is a variant of GaAs field effect transistor (FET) technology that offers substantially better performance than standard metal-semiconductor field-effect transistor (MESFET) devices.
A HEMT includes an undoped semiconductor (e.g., GaAs or an alloy thereof) channel with a thin doped layer of semiconductor (e.g., AlGaAs) between the channel and metal gate. The doped layer furnishes the carriers for the channel. Among other benefits, the electron mobility in the channel is higher in the HEMT than in a MESFET, because there are substantially no dopant ions in the channel to scatter carriers. This results in a two-dimensional electron gas (2DEG, also referred to as the channel charge), which is formed along the heterointerface. Among other applications, GaAs based HEMTs have become the standard for signal amplification in civil and military radar, handset cellular, and satellite communications. GaAs has a higher electron mobility and a lower source resistance than Si, which allows GaAs based devices to function at higher frequencies.
In many known HEMT devices, the gate forms a Schottky barrier with the semiconductor. Increasing the forward bias on the device increases the gate current, which in turn limits the voltage range of the device. In particular, increased gate current leads to a non-linear output and deleterious effects such as spurious frequencies. As will be appreciated, in many applications of HEMT devices, such as in communication devices, non-linear effects are undesirable.
In an effort to reduce the gate current, application of an oxide layer between the gate metal and the semiconductor has been considered. While useful to this end, many known oxide deposition techniques are above accepted temperature tolerances in III-V semiconductor processing. For example, photoresists and device features such as alloyed contacts and organic spin-on dielectrics, are unable to withstand the temperatures required to provide many known oxides. This leads to certain shortcomings and undesired results. Among other deleterious effects, in fabricating double-recess HEMT devices by such a known method, the need to apply remove a first resist and apply a second resist to form the recess for the gate can result in misalignment of the gate over the channel.
What is needed, therefore, is a method of fabricating III-V MOS devices that overcomes at least the shortcomings described.